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{{Event | {{Event | ||
|Acronym=MICRO 2020 | |Acronym=MICRO 2020 | ||
| − | |Title= | + | |Title=IEEE/ACM International Symposium on Microarchitecture |
| + | |Ordinal=53 | ||
| + | |In Event Series=Event Series:MICRO | ||
| + | |Single Day Event=no | ||
| + | |Start Date=2020/10/17 | ||
| + | |End Date=2020/10/21 | ||
| + | |Event Status=as scheduled | ||
| + | |Event Mode=online | ||
| + | |Academic Field=Computer Architecture | ||
| + | |Official Website=https://www.microarch.org/micro53/ | ||
|Type=Conference | |Type=Conference | ||
| − | |||
|Twitter account=@MicroArchConf | |Twitter account=@MicroArchConf | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
|has general chair=Dimitris Gizopoulos | |has general chair=Dimitris Gizopoulos | ||
|has program chair=Jun Yang, Mattan Erez | |has program chair=Jun Yang, Mattan Erez | ||
| Line 15: | Line 18: | ||
|pageEditor=User:Curator 19 | |pageEditor=User:Curator 19 | ||
|contributionType=1 | |contributionType=1 | ||
| − | |||
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}} | }} | ||
| + | {{Event Deadline | ||
| + | |Notification Deadline=2020/07/07 | ||
| + | |Abstract Deadline=2020/04/10 | ||
| + | |Paper Deadline=2020/04/17 | ||
| + | }} | ||
| + | {{Organizer | ||
| + | |Contributor Type=organization | ||
| + | |Organization=Technical Committee on Microprogramming and Microarchitecture, IEEE Computer Society | ||
| + | }} | ||
| + | {{Organizer | ||
| + | |Contributor Type=organization | ||
| + | |Organization=Special Interest Group on Microarchitecture, Association for Computing Machinery | ||
| + | }} | ||
| + | {{Organizer | ||
| + | |Contributor Type=organization | ||
| + | |Organization=Department of Informatics and Telecommunications, National and Kapodistrian University of Athens | ||
| + | }} | ||
| + | {{Event Metric}} | ||
| + | {{S Event}} | ||
'''MICRO 2020''' | '''MICRO 2020''' | ||
'''53rd IEEE/ACM International Symposium on Microarchitecture''' | '''53rd IEEE/ACM International Symposium on Microarchitecture''' | ||
| Line 34: | Line 52: | ||
==TOPCIS== | ==TOPCIS== | ||
We invite original paper submissions related to (but not limited to) the following topics: | We invite original paper submissions related to (but not limited to) the following topics: | ||
| − | * Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, security, cost, complexity, programmer productivity, predictability, quality of service, reliability, dependability, scalability, etc. | + | *Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, security, cost, complexity, programmer productivity, predictability, quality of service, reliability, dependability, scalability, etc. |
| − | * Architectures for emerging application domains such as deep learning, machine learning, relational computation, neuromorphic, quantum, etc. | + | *Architectures for emerging application domains such as deep learning, machine learning, relational computation, neuromorphic, quantum, etc. |
| − | * Accelerator designs and heterogeneous architectures including system-on-chip architectures, application specific fixed function, programmable, reconfigurable, near- data and in-memory accelerators, etc. | + | *Accelerator designs and heterogeneous architectures including system-on-chip architectures, application specific fixed function, programmable, reconfigurable, near- data and in-memory accelerators, etc. |
| − | * Architectural support for security, side-channel attacks and mitigation, privacy preserving computation, IoT/Cloud/Cyber-Physical-System security, security primitives, trusted execution environments, etc. | + | *Architectural support for security, side-channel attacks and mitigation, privacy preserving computation, IoT/Cloud/Cyber-Physical-System security, security primitives, trusted execution environments, etc. |
| − | * Architecture, microarchitecture and/or compiler optimizations for graphics processor units (GPUs) or other programmable accelerators | + | *Architecture, microarchitecture and/or compiler optimizations for graphics processor units (GPUs) or other programmable accelerators |
| − | * Microarchitecture and compiler techniques for optimizing the memory hierarchy, analysis of new memory hierarchies, emerging architectures based on new memory technologies | + | *Microarchitecture and compiler techniques for optimizing the memory hierarchy, analysis of new memory hierarchies, emerging architectures based on new memory technologies |
| − | * Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, many-core, etc. | + | *Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, many-core, etc. |
| − | * Processor, memory, interconnect, and storage architectures | + | *Processor, memory, interconnect, and storage architectures |
| − | * Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP) | + | *Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP) |
| − | * Microarchitecture techniques to better support system software, programming languages, programmability, and compilation | + | *Microarchitecture techniques to better support system software, programming languages, programmability, and compilation |
| − | * Advanced software/hardware speculation and prediction schemes | + | *Advanced software/hardware speculation and prediction schemes |
| − | * Microarchitecture modeling and simulation methodology | + | *Microarchitecture modeling and simulation methodology |
| − | * Low-power, high-performance, and cost/complexity-efficient architectures | + | *Low-power, high-performance, and cost/complexity-efficient architectures |
| − | * Architectures for emerging embedded platforms, including smartphones, automotive, server/cloud, etc. | + | *Architectures for emerging embedded platforms, including smartphones, automotive, server/cloud, etc. |
| − | * Architecture and/or compiler optimizations for embedded processors, DSPs, ASIPs (network processors, multimedia, wireless, etc.) | + | *Architecture and/or compiler optimizations for embedded processors, DSPs, ASIPs (network processors, multimedia, wireless, etc.) |
| − | * Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads | + | *Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads |
==Committees== | ==Committees== | ||
| − | '''General | + | '''General Chair''' |
| − | * Dimitris Gizopoulos, National and Kapodistrian University of Athens | + | *Dimitris Gizopoulos, National and Kapodistrian University of Athens |
| − | '''Program Co- | + | '''Program Co-Chairs''' |
| − | * Jun Yang, University of Pittsburgh | + | *Jun Yang, University of Pittsburgh |
| − | * Mattan Erez, University of Texas at Austin | + | *Mattan Erez, University of Texas at Austin |
| − | '''Tutorials and Workshops Co- | + | '''Tutorials and Workshops Co-Chairs''' |
| − | * Boris Grot, University of Edinburgh | + | *Boris Grot, University of Edinburgh |
| − | * Dionisios Pnevmatikatos, National Technical University of Athens | + | *Dionisios Pnevmatikatos, National Technical University of Athens |
| − | '''Finance | + | '''Finance Chair''' |
| − | * Georgios Karakonstantis, Queen’s University Belfast | + | *Georgios Karakonstantis, Queen’s University Belfast |
| − | '''Web | + | '''Web Chair''' |
| − | * Saugata Ghose,Carnegie Mellon University | + | *Saugata Ghose,Carnegie Mellon University |
| − | '''Fundraising Committee Co- | + | '''Fundraising Committee Co-Chairs''' |
| − | * Yanos Sazeides, University of Cyprus | + | *Yanos Sazeides, University of Cyprus |
| − | * | + | *Christina Delimitrou, Cornell University |
| − | * Koji Inoue,Kyushu University | + | *Koji Inoue,Kyushu University |
| − | '''Industry Liaison Committee Co- | + | '''Industry Liaison Committee Co-Chairs''' |
| − | * Carole-Jean Wu, Facebook / Arizona State University | + | *Carole-Jean Wu, Facebook / Arizona State University |
| − | * Aamer Jaleel, Nvidia | + | *Aamer Jaleel, Nvidia |
| − | * Emre Ozer, Arm | + | *Emre Ozer, Arm |
| − | * Lisa Wu Wills, Duke University | + | *Lisa Wu Wills, Duke University |
| − | '''Publications Co- | + | '''Publications Co-Chairs''' |
| − | * Stefanos Kaxiras, Uppsala University | + | *Stefanos Kaxiras, Uppsala University |
| − | * George Papadimitriou, National and Kapodistrian University of Athens | + | *George Papadimitriou, National and Kapodistrian University of Athens |
| − | '''Publicity Co- | + | '''Publicity Co-Chairs''' |
| − | * Dimitrios Skarlatos, University of Illinois at Urbana- | + | *Dimitrios Skarlatos, University of Illinois at Urbana-Champaign |
| − | * Jingwen Leng, Shanghai Jiao Tong University | + | *Jingwen Leng, Shanghai Jiao Tong University |
| − | * Athanasios | + | *Athanasios Chatzidimitriou, National and Kapodistrian University of Athens |
| − | '''Registration | + | '''Registration Chair''' |
| − | * Mihalis Maniatakos, New York University, Abu Dhabi | + | *Mihalis Maniatakos, New York University, Abu Dhabi |
| − | '''Student Research Competition Co- | + | '''Student Research Competition Co-Chairs''' |
| − | * Yasuko Eckert, AMD | + | *Yasuko Eckert, AMD |
| − | * Osman Unsal, Barcelona Supercomputing Center | + | *Osman Unsal, Barcelona Supercomputing Center |
| − | '''Travel Award Co- | + | '''Travel Award Co-Chairs''' |
| − | * Omer Khan, University of Connecticut | + | *Omer Khan, University of Connecticut |
| − | Ashish Venkat, Virginia Tech | + | Ashish Venkat, Virginia Tech |
'''Local Arrangements''' | '''Local Arrangements''' | ||
| − | * Antonis Paschalis, National and Kapodistrian University of Athens | + | *Antonis Paschalis, National and Kapodistrian University of Athens |
| − | * Spyros Xergias, National and Kapodistrian University of Athens | + | *Spyros Xergias, National and Kapodistrian University of Athens |
Latest revision as of 11:53, 17 November 2022
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Venue
Warning: Venue is missing. The map might not show the exact location.
MICRO 2020 53rd IEEE/ACM International Symposium on Microarchitecture
The International Symposium on Microarchitecture® (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems. The goal of MICRO is to bring together researchers in the fields of microarchitecture, compilers, and systems for technical exchange. The MICRO community has enjoyed having close interaction between academic researchers and industrial designers—we aim to continue and strengthen this longstanding tradition at the 53rd MICRO in Athens, Greece.
Important Dates
* HotCRP Submission Site Opens: March 27, 2020 * Abstract Deadline: April 10, 2020 at 11:59 PM PDT * Full Paper Deadline: April 17, 2020 at 11:59 PM PDT * Rebuttal/Optional Revision: June 6–17, 2020 * Notification: July 7, 2020
TOPCIS
We invite original paper submissions related to (but not limited to) the following topics:
- Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, security, cost, complexity, programmer productivity, predictability, quality of service, reliability, dependability, scalability, etc.
- Architectures for emerging application domains such as deep learning, machine learning, relational computation, neuromorphic, quantum, etc.
- Accelerator designs and heterogeneous architectures including system-on-chip architectures, application specific fixed function, programmable, reconfigurable, near- data and in-memory accelerators, etc.
- Architectural support for security, side-channel attacks and mitigation, privacy preserving computation, IoT/Cloud/Cyber-Physical-System security, security primitives, trusted execution environments, etc.
- Architecture, microarchitecture and/or compiler optimizations for graphics processor units (GPUs) or other programmable accelerators
- Microarchitecture and compiler techniques for optimizing the memory hierarchy, analysis of new memory hierarchies, emerging architectures based on new memory technologies
- Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, many-core, etc.
- Processor, memory, interconnect, and storage architectures
- Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP)
- Microarchitecture techniques to better support system software, programming languages, programmability, and compilation
- Advanced software/hardware speculation and prediction schemes
- Microarchitecture modeling and simulation methodology
- Low-power, high-performance, and cost/complexity-efficient architectures
- Architectures for emerging embedded platforms, including smartphones, automotive, server/cloud, etc.
- Architecture and/or compiler optimizations for embedded processors, DSPs, ASIPs (network processors, multimedia, wireless, etc.)
- Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads
Committees
General Chair
- Dimitris Gizopoulos, National and Kapodistrian University of Athens
Program Co-Chairs
- Jun Yang, University of Pittsburgh
- Mattan Erez, University of Texas at Austin
Tutorials and Workshops Co-Chairs
- Boris Grot, University of Edinburgh
- Dionisios Pnevmatikatos, National Technical University of Athens
Finance Chair
- Georgios Karakonstantis, Queen’s University Belfast
Web Chair
- Saugata Ghose,Carnegie Mellon University
Fundraising Committee Co-Chairs
- Yanos Sazeides, University of Cyprus
- Christina Delimitrou, Cornell University
- Koji Inoue,Kyushu University
Industry Liaison Committee Co-Chairs
- Carole-Jean Wu, Facebook / Arizona State University
- Aamer Jaleel, Nvidia
- Emre Ozer, Arm
- Lisa Wu Wills, Duke University
Publications Co-Chairs
- Stefanos Kaxiras, Uppsala University
- George Papadimitriou, National and Kapodistrian University of Athens
Publicity Co-Chairs
- Dimitrios Skarlatos, University of Illinois at Urbana-Champaign
- Jingwen Leng, Shanghai Jiao Tong University
- Athanasios Chatzidimitriou, National and Kapodistrian University of Athens
Registration Chair
- Mihalis Maniatakos, New York University, Abu Dhabi
Student Research Competition Co-Chairs
- Yasuko Eckert, AMD
- Osman Unsal, Barcelona Supercomputing Center
Travel Award Co-Chairs
- Omer Khan, University of Connecticut
Ashish Venkat, Virginia Tech Local Arrangements
- Antonis Paschalis, National and Kapodistrian University of Athens
- Spyros Xergias, National and Kapodistrian University of Athens
