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{{Event | {{Event | ||
|Acronym=MICRO 2019 | |Acronym=MICRO 2019 | ||
| − | |Title= | + | |Title=IEEE/ACM International Symposium on Microarchitecture |
| − | | | + | |Ordinal=52 |
| − | | | + | |In Event Series=Event Series:MICRO |
| + | |Single Day Event=no | ||
| + | |Start Date=2019/10/12 | ||
| + | |End Date=2019/10/16 | ||
| + | |Event Status=as scheduled | ||
| + | |Event Mode=on site | ||
|City=Columbus | |City=Columbus | ||
|Region=Ohio | |Region=Ohio | ||
|Country=Country:US | |Country=Country:US | ||
| + | |Academic Field=Computer Architecture | ||
| + | |Official Website=https://www.microarch.org/micro52/ | ||
| + | |Type=Conference | ||
|has general chair=Radu Teodorescu, DK Panda | |has general chair=Radu Teodorescu, DK Panda | ||
|has program chair=Tor Aamodt, Reetuparna Das | |has program chair=Tor Aamodt, Reetuparna Das | ||
| Line 15: | Line 23: | ||
|pageEditor=User:Curator 52 | |pageEditor=User:Curator 52 | ||
|contributionType=1 | |contributionType=1 | ||
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}} | }} | ||
{{Event Deadline | {{Event Deadline | ||
| − | | | + | |Notification Deadline=2019/07/25 |
| + | |Abstract Deadline=2019/03/29 | ||
| + | |Paper Deadline=2019/04/05 | ||
| + | }} | ||
| + | {{Organizer | ||
| + | |Contributor Type=organization | ||
| + | |Organization=Technical Committee on Microprogramming and Microarchitecture, IEEE Computer Society | ||
| + | }} | ||
| + | {{Organizer | ||
| + | |Contributor Type=organization | ||
| + | |Organization=Special Interest Group on Microarchitecture, Association for Computing Machinery | ||
}} | }} | ||
{{Event Metric | {{Event Metric | ||
| Line 35: | Line 47: | ||
==Important Dates== | ==Important Dates== | ||
| − | * Abstract Deadline: March 29, 2019 at 4:59 PM PDT | + | *Abstract Deadline: March 29, 2019 at 4:59 PM PDT |
| − | * Full Paper Deadline: April 5, 2019 at 4:59 PM PDT | + | *Full Paper Deadline: April 5, 2019 at 4:59 PM PDT |
| − | * First Round Decisions: June 1, 2019 | + | *First Round Decisions: June 1, 2019 |
| − | * Reviews Released: June 26, 2019 | + | *Reviews Released: June 26, 2019 |
| − | * Rebuttal/Response Deadline: July 3, 2019 at 8:59 PM PDT | + | *Rebuttal/Response Deadline: July 3, 2019 at 8:59 PM PDT |
| − | * Notification: July 25, 2019 | + | *Notification: July 25, 2019 |
==Topics== | ==Topics== | ||
We invite original paper submissions related to (but not limited to) the following topics: | We invite original paper submissions related to (but not limited to) the following topics: | ||
| − | * Architectures for emerging application domains such as deep learning, machine learning, relational computation, neuromorphic, quantum, etc. | + | *Architectures for emerging application domains such as deep learning, machine learning, relational computation, neuromorphic, quantum, etc. |
| − | * Accelerator designs and heterogeneous architectures including system-on-chip architectures, application specific fixed function, programmable, reconfigurable, near-data and in-memory accelerators, etc. | + | *Accelerator designs and heterogeneous architectures including system-on-chip architectures, application specific fixed function, programmable, reconfigurable, near-data and in-memory accelerators, etc. |
| − | * Architectural support for security, side-channel attacks and mitigation, privacy preserving computation, IoT/Cloud/Cyber-Physical-System security, security primitives, trusted execution environments, etc. | + | *Architectural support for security, side-channel attacks and mitigation, privacy preserving computation, IoT/Cloud/Cyber-Physical-System security, security primitives, trusted execution environments, etc. |
| − | * Architecture, microarchitecture and/or compiler optimizations for graphics processor units (GPUs) or other programmable accelerators | + | *Architecture, microarchitecture and/or compiler optimizations for graphics processor units (GPUs) or other programmable accelerators |
| − | * Microarchitecture and compiler techniques for optimizing the memory hierarchy, analysis of new memory hierarchies, emerging architectures based on new memory technologies | + | *Microarchitecture and compiler techniques for optimizing the memory hierarchy, analysis of new memory hierarchies, emerging architectures based on new memory technologies |
| − | * Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, security, cost, complexity, programmer productivity, predictability, quality of service, reliability, dependability, scalability, etc. | + | *Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, security, cost, complexity, programmer productivity, predictability, quality of service, reliability, dependability, scalability, etc. |
| − | * Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, many-core, etc. | + | *Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, many-core, etc. |
| − | * Processor, memory, interconnect, and storage architectures | + | *Processor, memory, interconnect, and storage architectures |
| − | * Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP) | + | *Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP) |
| − | * Microarchitecture techniques to better support system software, programming languages, programmability, and compilation | + | *Microarchitecture techniques to better support system software, programming languages, programmability, and compilation |
| − | * Advanced software/hardware speculation and prediction schemes | + | *Advanced software/hardware speculation and prediction schemes |
| − | * Microarchitecture modeling and simulation methodology | + | *Microarchitecture modeling and simulation methodology |
| − | * Low-power, high-performance, and cost/complexity-efficient architectures | + | *Low-power, high-performance, and cost/complexity-efficient architectures |
| − | * Architectures for emerging embedded platforms, including smartphones, automotive, server/cloud, etc. | + | *Architectures for emerging embedded platforms, including smartphones, automotive, server/cloud, etc. |
| − | * Architecture and/or compiler optimizations for embedded processors, DSPs, ASIPs (network processors, multimedia, wireless, etc.) | + | *Architecture and/or compiler optimizations for embedded processors, DSPs, ASIPs (network processors, multimedia, wireless, etc.) |
| − | * Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads | + | *Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads |
Submissions should follow the guidelines and formatting rules specified on the conference website. Papers that violate these guidelines and rules may be returned to author(s) without review. | Submissions should follow the guidelines and formatting rules specified on the conference website. Papers that violate these guidelines and rules may be returned to author(s) without review. | ||
Latest revision as of 11:57, 17 November 2022
Deadlines
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Metrics
Submitted Papers
344
Accepted Papers
79
Venue
Columbus, Ohio, United States of America
Warning: Venue is missing. The map might not show the exact location.
Call for Papers
The International Symposium on Microarchitecture® (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems. The goal of MICRO is to bring together researchers in the fields of microarchitecture, compilers, and systems for technical exchange. The MICRO community has enjoyed having close interaction between academic researchers and industrial designers—we aim to continue and strengthen this longstanding tradition at the 52nd MICRO in Columbus, Ohio.
Important Dates
- Abstract Deadline: March 29, 2019 at 4:59 PM PDT
- Full Paper Deadline: April 5, 2019 at 4:59 PM PDT
- First Round Decisions: June 1, 2019
- Reviews Released: June 26, 2019
- Rebuttal/Response Deadline: July 3, 2019 at 8:59 PM PDT
- Notification: July 25, 2019
Topics
We invite original paper submissions related to (but not limited to) the following topics:
- Architectures for emerging application domains such as deep learning, machine learning, relational computation, neuromorphic, quantum, etc.
- Accelerator designs and heterogeneous architectures including system-on-chip architectures, application specific fixed function, programmable, reconfigurable, near-data and in-memory accelerators, etc.
- Architectural support for security, side-channel attacks and mitigation, privacy preserving computation, IoT/Cloud/Cyber-Physical-System security, security primitives, trusted execution environments, etc.
- Architecture, microarchitecture and/or compiler optimizations for graphics processor units (GPUs) or other programmable accelerators
- Microarchitecture and compiler techniques for optimizing the memory hierarchy, analysis of new memory hierarchies, emerging architectures based on new memory technologies
- Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, security, cost, complexity, programmer productivity, predictability, quality of service, reliability, dependability, scalability, etc.
- Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, many-core, etc.
- Processor, memory, interconnect, and storage architectures
- Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP)
- Microarchitecture techniques to better support system software, programming languages, programmability, and compilation
- Advanced software/hardware speculation and prediction schemes
- Microarchitecture modeling and simulation methodology
- Low-power, high-performance, and cost/complexity-efficient architectures
- Architectures for emerging embedded platforms, including smartphones, automotive, server/cloud, etc.
- Architecture and/or compiler optimizations for embedded processors, DSPs, ASIPs (network processors, multimedia, wireless, etc.)
- Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads
Submissions should follow the guidelines and formatting rules specified on the conference website. Papers that violate these guidelines and rules may be returned to author(s) without review.
