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{{Event | {{Event | ||
|Acronym=MICRO 2018 | |Acronym=MICRO 2018 | ||
| − | |Title= | + | |Title=IEEE/ACM International Symposium on Microarchitecture |
| − | | | + | |Ordinal=51 |
| − | | | + | |In Event Series=Event Series:MICRO |
| + | |Single Day Event=no | ||
| + | |Start Date=2018/10/20 | ||
| + | |End Date=2018/10/24 | ||
| + | |Event Status=as scheduled | ||
| + | |Event Mode=on site | ||
|City=Fukuoka City | |City=Fukuoka City | ||
|Country=Country:JP | |Country=Country:JP | ||
| + | |Academic Field=Computer Architecture | ||
| + | |Official Website=https://www.microarch.org/micro51/ | ||
| + | |Type=Conference | ||
|has general chair=Koji Inoue, Mark Oskin | |has general chair=Koji Inoue, Mark Oskin | ||
|has program chair=Hyesoon Kim, Sudhakar Yalamanchili | |has program chair=Hyesoon Kim, Sudhakar Yalamanchili | ||
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|pageEditor=User:Curator 52 | |pageEditor=User:Curator 52 | ||
|contributionType=1 | |contributionType=1 | ||
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}} | }} | ||
{{Event Deadline | {{Event Deadline | ||
| − | | | + | |Notification Deadline=2018/07/18 |
| + | |Abstract Deadline=2018/03/30 | ||
| + | |Paper Deadline=2018/04/06 | ||
}} | }} | ||
{{Event Metric | {{Event Metric | ||
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==Important Dates== | ==Important Dates== | ||
| − | * Abstract: March 30th, 2018 at 11:59pm EDT | + | *Abstract: March 30th, 2018 at 11:59pm EDT |
| − | * Full Paper: April 6th, 2018 at 11:59pm EDT | + | *Full Paper: April 6th, 2018 at 11:59pm EDT |
| − | * Rebuttal and Response: June 27th - July 3rd 2018 | + | *Rebuttal and Response: June 27th - July 3rd 2018 |
| − | * Notification: July 18th 2018 | + | *Notification: July 18th 2018 |
==Topics== | ==Topics== | ||
We invite original paper submissions related to (but not limited to) the following topics: | We invite original paper submissions related to (but not limited to) the following topics: | ||
| − | * Processor, memory, interconnect, and storage architectures. | + | *Processor, memory, interconnect, and storage architectures. |
| − | * Microarchitecture and compiler techniques for optimizing the memory hierarchy, analysis of new memory hierarchies, emerging architectures based on new memory technologies. | + | *Microarchitecture and compiler techniques for optimizing the memory hierarchy, analysis of new memory hierarchies, emerging architectures based on new memory technologies. |
| − | * Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, cost, complexity, predictability, quality of service, reliability, dependability, security, scalability, programmer productivity, etc. | + | *Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, cost, complexity, predictability, quality of service, reliability, dependability, security, scalability, programmer productivity, etc. |
| − | * Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, many-core, etc. | + | *Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, many-core, etc. |
| − | * Architectures for emerging application domains such as deep learning, machine learning, relational computation, neuromorphic, quantum, etc. | + | *Architectures for emerging application domains such as deep learning, machine learning, relational computation, neuromorphic, quantum, etc. |
| − | * Accelerator designs and heterogeneous architectures including system-on-chip architectures, application specific fixed function, programmable, near-data and in-memory accelerators, etc. | + | *Accelerator designs and heterogeneous architectures including system-on-chip architectures, application specific fixed function, programmable, near-data and in-memory accelerators, etc. |
| − | * Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP). | + | *Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP). |
| − | * Compiler optimizations and microarchitecture techniques for heterogeneous architectures including CPU+GPUs, GPUs, SoCs, and programmable accelerators. | + | *Compiler optimizations and microarchitecture techniques for heterogeneous architectures including CPU+GPUs, GPUs, SoCs, and programmable accelerators. |
| − | * Microarchitecture techniques to better support system software, programming languages, programmability, and compilation. | + | *Microarchitecture techniques to better support system software, programming languages, programmability, and compilation. |
| − | * Architectures and compilers for embedded processors, DSPs, GPUs, ASIPs (network processors, multimedia, wireless, etc.). | + | *Architectures and compilers for embedded processors, DSPs, GPUs, ASIPs (network processors, multimedia, wireless, etc.). |
| − | * Low-power, high-performance, and cost/complexity-efficient architectures. | + | *Low-power, high-performance, and cost/complexity-efficient architectures. |
| − | * Architectures for emerging embedded platforms, including smartphones, automotive, server/cloud, etc. | + | *Architectures for emerging embedded platforms, including smartphones, automotive, server/cloud, etc. |
| − | * Advanced software/hardware speculation and prediction schemes. | + | *Advanced software/hardware speculation and prediction schemes. |
| − | * Microarchitecture modeling and simulation methodology. | + | *Microarchitecture modeling and simulation methodology. |
| − | * Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads. | + | *Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads. |
Submissions should follow the guidelines and formatting rules specified on the conference website. Papers that violate these guidelines and rules may be returned to author(s) without review. | Submissions should follow the guidelines and formatting rules specified on the conference website. Papers that violate these guidelines and rules may be returned to author(s) without review. | ||
Revision as of 13:59, 2 November 2022
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Metrics
Submitted Papers
351
Accepted Papers
74
Venue
Grand Hyatt Fukuoka, Fukuoka City, Japan
Call for Papers
The International Symposium on Microarchitecture ® (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems. The goal of MICRO is to bring together researchers in the fields of microarchitecture, compilers, and systems for technical exchange. The MICRO community has enjoyed having close interaction between academic researchers and industrial designers—we aim to continue and strengthen this longstanding tradition at the 51st MICRO in Fukuoka, Japan.
Important Dates
- Abstract: March 30th, 2018 at 11:59pm EDT
- Full Paper: April 6th, 2018 at 11:59pm EDT
- Rebuttal and Response: June 27th - July 3rd 2018
- Notification: July 18th 2018
Topics
We invite original paper submissions related to (but not limited to) the following topics:
- Processor, memory, interconnect, and storage architectures.
- Microarchitecture and compiler techniques for optimizing the memory hierarchy, analysis of new memory hierarchies, emerging architectures based on new memory technologies.
- Hardware, software, and hybrid techniques for improving system performance, energy-efficiency, cost, complexity, predictability, quality of service, reliability, dependability, security, scalability, programmer productivity, etc.
- Architectures for instruction-level, thread-level, and memory-level parallelism: superscalar, VLIW, data-parallel, multithreaded, multicore, many-core, etc.
- Architectures for emerging application domains such as deep learning, machine learning, relational computation, neuromorphic, quantum, etc.
- Accelerator designs and heterogeneous architectures including system-on-chip architectures, application specific fixed function, programmable, near-data and in-memory accelerators, etc.
- Compiler and microarchitectural techniques for parallelism (ILP, TLP, MLP).
- Compiler optimizations and microarchitecture techniques for heterogeneous architectures including CPU+GPUs, GPUs, SoCs, and programmable accelerators.
- Microarchitecture techniques to better support system software, programming languages, programmability, and compilation.
- Architectures and compilers for embedded processors, DSPs, GPUs, ASIPs (network processors, multimedia, wireless, etc.).
- Low-power, high-performance, and cost/complexity-efficient architectures.
- Architectures for emerging embedded platforms, including smartphones, automotive, server/cloud, etc.
- Advanced software/hardware speculation and prediction schemes.
- Microarchitecture modeling and simulation methodology.
- Insightful experimental and comparative evaluation and analysis of existing microarchitectures, hardware/software mechanisms and workloads.
Submissions should follow the guidelines and formatting rules specified on the conference website. Papers that violate these guidelines and rules may be returned to author(s) without review.
